The invention uses various materials which are electrically either conductive, insulating, or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
The storage capacity of a memory chip is dependent on the number of memory cells in the chip. Dynamic random-access memory DRAM cells are comprised of two main components, a field effect transistor (FET) and a storage capacitor. The field effect transistor (FET) and storage capacitor are generally located in a horizontal plane formed mostly on the surface of the chip. In DRAM cells utilizing a conventional planar capacitor, such as the one depicted in FIG. 1, a large chip area is dedicated to the planar capacitor and field effect transistor (FET).
Recently, research has been directed to three-dimensional Complementary Metal-Oxide Semiconductor CMOS integration to improve component density in memory chips. Three-dimensional integration significantly increases the circuit densities of monolithically integrated systems. One such three-dimensional technique for a transistor-capacitor DRAM cell involves the creation of "trench" capacitors in the cell substrate. FIG. 2 depicts a DRAM memory cell formed with a typical trench capacitor. Similar in concept to the planar capacitor of FIG. 1, a vertical trench is employed to form the capacitor plate with the expenditure of less surface area.
A second three-dimensional technique is to stack a capacitor on top of the transistor. In this type of stacked structure, the clip area is shirred between the transistor and the capacitor as seen in FIG. 3. In both cases (trench capacitor or stacked structure), standard silicon technology can be utilized to form the circuits.
Some research has also been done on structures which includes a CMOS invertor with the PMOS stacked on top of the NMOS, and a shared gate sandwiched between the two devices. The top substrate of the stacked device is formed of polysilicon. A problem with the use of polysilicon in this application is that, because of the high recrystallization temperature of polysilicon, large processing temperature gradients are required. These temperature gradients induce large defect densities in the cell structure.
One recent technique for developing a stacked or intermediate active monocrystalline device layer is by selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of monocrystalline silicon. These techniques involve relatively low processing temperatures (i.e., 900.degree. C.) so that fewer cell defects are formed.
In general, (SEG) and (ELO) involve low temperature epitaxy to limit silicon growth and produce intermediate substrates or device islands. To produce (SEG), seed contacts are opened on an oxidized silicon substrate. Epitaxial growth is then initiated selectively in the seed contacts and progresses vertically until it reaches the level of the oxide and then grows laterally over the insulating oxide film (ELO). This produces a single crystal silicon layer. This layer can then be planarized by known techniques such as chemical-mechanical polishing. Such SEG/ELO techniques are described in U.S. Pat. No. 4,760,036 to Schubert and in the technical article "Three-Dimensional CMOS Integration" contained in IEEE Circuits and Devices Magazine, September 1990.
It is not necessary to planarize an intermediate substrate if the (ELO) is confined inside cavities, such that lateral growth is maintained while restricting vertical growth. This (SEG) technique is termed "confined lateral selective epitaxial growth" (CLSEG).
The present invention is directed to a novel three-dimensional DRAM cell in which a (CLSEG) process is utilized to form an intermediate substrate or island. An access transistor can be formed on this intermediate substrate, stacked upon an access transistor previously formed on the main substrate. This forms a double-memory cell and for a given chip area more than doubles the memory capacity.